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integrated circuit systems, inc. ics98ulpa877a advance information 1177c?05/23/07 1.8v low-power wide-range frequency clock driver pin configuration 40-pin mlf recommended application: ? ddr2 memory modules / zero delay board fan out ? provides complete ddr2 dimm logic solution product description/features: ? low skew, low jitter pll clock driver ? 1 to 10 differential clock distribution (sstl_18) ? feedback pins for input to output synchronization ? spread spectrum tolerant inputs ? auto pd when input signal is at a certain logic state switching characteristics: ? period jitter: 40ps (ddr2-400/533) 30ps (ddr2-667/800) ? half-period jitter: 60ps (ddr2-400/533) 50ps (ddr2-667/800) ? output - output skew: 40ps (ddr2-400/533) 30ps (ddr2-667/800) ? cycle - cycle jitter 40ps 52-ball bga top view block diagram advance information documents contain information on products in the formative or design phase development. characteristic data and other specific ations are design goals. ics reserves the right to change or discontinue these products without notice. third party brands and names are the property of their respective owners. fboutt fboutc fbin_int fbin_inc pll clk_int clk_inc power down and test mode logic ld av dd oe os ld or oe ld, os, or oe pll bypass 10k -100k clkt0 clkc0 clkt1 clkc1 clkt2 clkc2 clkt3 clkc3 clkt4 clkc4 clkt5 clkc5 clkt6 clkc6 clkt7 clkc7 clkt8 clkc8 clkt9 clkc9 (1) note: 1. the logic detect (ld) powers down the device when a logic low is applied to both clk_int and clk_inc. b c d e f g h j k a 123456 v d d q 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 3 2 3 1 v d d q 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 v d d q v d d q v ddq fb_int fb_inc fboutc 30 29 28 27 26 25 24 23 22 21 fboutt oe os v ddq gnd v ddq agnd av dd clk_int clk_inc v ddq 2 3 4 5 6 7 8 1 9 10 v ddq clkc2 clkt2 clkc7 clkt7 c l k c 3 c l k t 3 c l k c 4 c l k t 4 c l k c 9 c l k t 9 c l k c 8 c l k t 8 c l k c 1 c l k t 1 c l k c 0 c l k t 0 c l k c 5 c l k t 5 c l k c 6 c l k t 6 12345 6 a clkt1 clkt0 clkc0 clkc5 clkt5 clkt6 b clkc1 gnd gnd gnd gnd clkc6 c clkc2 gnd nb nb gnd clkc7 d clkt2 vddq vddq vddq os clkt7 e clk_int vddq nb nb vddq fb_int f clk_inc vddq nb nb oe fb_inc g agnd vddq vddq vddq vddq fb_outc h avdd gnd nb nb gnd fb_outt j clkt3 gnd gnd gnd gnd clkt8 k clkc3 clkc4 clkt4 clkt9 clkc9 clkc8
2 ics98ulpa877a advance information 1177c?05/23/07 pin descriptions l a n i m r e t e m a n n o i t p i r c s e d l a c i r t c e l e s c i t s i r e t c a r a h c d n g ad n u o r g g o l a n a d n u o r g v a d d r e w o p g o l a n a l a n i m o n v 8 . 1 t n i _ k l cr o t s i s e r n w o d l l u p ) m h o k 0 0 1 - k 0 1 ( a h t i w t u p n i k c o l c t u p n i l a i t n e r e f f i d c n i _ k l c r o t s i s e r n w o d l l u p ) m h o k 0 0 1 - k 0 1 ( a h t i w t u p n i k c o l c y r a t n e l p m o c t u p n i l a i t n e r e f f i d t n i _ b ft u p n i k c o l c k c a b d e e f t u p n i l a i t n e r e f f i d c n i _ b ft u p n i k c o l c k c a b d e e f y r a t n e m e l p m o c t u p n i l a i t n e r e f f i d t t u o _ b ft u p t u o k c o l c k c a b d e e f t u p t u o l a i t n e r e f f i d c t u o _ b ft u p t u o k c o l c k c a b d e e f y r a t n e m e l p m o c t u p t u o l a i t n e r e f f i d e o) s u o n o r h c n y s a ( e l b a n e t u p t u o t u p n i s o m c v l s ov r o d n g o t d e i t ( t c e l e s t u p t u o q d d )t u p n i s o m c v l d n gd n u o r g d n u o r g v q d d r e w o p t u p t u o d n a c i g o l l a n i m o n v 8 . 1 ] 9 : 0 [ t k l cs t u p t u o k c o l c s t u p t u o l a i t n e r e f f i d ] 9 : 0 [ c k l cs t u p t u o k c o l c y r a t n e m e l p m o c s t u p t u o l a i t n e r e f f i d b nl l a b o n the pll clock buffer, ics98ulpa877a , is designed for a v ddq of 1.8 v, a av dd of 1.8 v and differential data input and output levels. package options include a plastic 52-ball vfbga and a 40-pin mlf. ics98ulpa877a is a zero delay buffer that distributes a differential clock input pair (clk_int, clk_inc) to ten differential pair of clock outputs (clkt[0:9], clkc[0:9]) and one differential pair feedback clock outputs (fb_outt, fboutc). the clock outputs are controlled by the input clocks (clk_int, clk_inc), the feedback clocks (fb_int, fb_inc), the lvcmos program pins (oe, os) and the analog power input (avdd). when oe is low, the outputs (except fb_outt/fb_outc) are disabled while the internal pll continues to maintain its locked-in frequency. os (output select) is a program pin that must be tied to gnd or v ddq . when os is high, oe will function as described above. when os is low, oe has no effect on clkt7/clkc7 (they are free running in addition to fb_outt/fb_outc). when av dd is grounded, the pll is turned off and bypassed for test purposes. when both clock signals (clk_int, clk_inc) are logic low, the device will enter a low power mode. an input logic detection circuit on the differential inputs, independent from the input buffers, will detect the logic low level and perform a low power state where all outputs, the feedback and the pll are off. when the inputs transition from both being logic low to being differential signals, the pll will be turned back on, the inputs and outputs will be enabled and the pll will obtain phase lock between the feedback clock pair (fb_int, fb_inc) and the input clock pair (clk_int, clk_inc) within the specified stabilization time t stab . the pll in ics98ulpa877a clock driver uses the input clocks (clk_int, clk_inc) and the feedback clocks (fb_int, fb_inc) to provide high-performance, low-skew, low-jitter output differential clocks (clkt[0:9], clkc[0:9]). ics98ulpa877a is also able to track spread spectrum clocking (ssc) for reduced emi.
3 ics98ulpa877a advance information 1177c?05/23/07 function table s t u p n is t u p t u o l l p d d v ae os ot n i _ k l cc n i _ k l ct k l cc k l ct t u o _ b fc t u o _ b f d n ghxl h l h l h f f o / d e s s a p y b d n ghxh l h l h l f f o / d e s s a p y b d n glhl h ) z ( l *) z ( l *lh f f o / d e s s a p y b d n gllh l , ) z ( l * 7 t k l c e v i t c a , ) z ( l * 7 c k l c e v i t c a h lf f o / d e s s a p y b ) m o n ( v 8 . 1lhlh ) z ( l *) z ( l *lh n o ) m o n ( v 8 . 1llhl , ) z ( l * 7 t k l c e v i t c a , ) z ( l * 7 c k l c e v i t c a hl n o ) m o n ( v 8 . 1hxlhlhlh n o ) m o n ( v 8 . 1hxhlhlhl n o ) m o n ( v 8 . 1xxll ) z ( l *) z ( l *) z ( l *) z ( l *f f o ) m o n ( v 8 . 1xxhh d e v r e s e r *l(z) means the outputs are disabled to a low stated meeting the i odl limit. ics98ulpa877a is available in commercial temperature range (0c to 70c) and industrial temperature range (-40c to +85c). see ordering information for details
4 ics98ulpa877a advance information 1177c?05/23/07 absolute maximum ratings supply voltage (vddq & avdd) . . . . . . . . . -0.5v to 2.5v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . gnd - 0.5v to v ddq + 0.5v ambient operating temperature . . . . . . . . . . -40c to +85c storage temperature . . . . . . . . . . . . . . . . . . . -65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. electrical characterist ics - input/supply/commo n output parameters commercial: ta = 0c - 70c; i ndustrial: ta = -40c - +85c; supply voltage avddq, vddq = 1.8 v +/ - 0.1v (unless otherwise stated) parameter symbol conditions min typ max units input high current ( clk_int, clk_inc ) i ih v i = v ddq or gnd 250 a input low current (oe, os, fb_int, fb_inc ) i il v i = v ddq or gnd 10 a output disabled low current i odl oe = l, v odl = 100mv 100 a i dd1.8 c l = 0pf @ 410mhz 300 ma i ddld c l = 0pf 500 a input clamp voltage v ik v ddq = 1.7v iin = -18ma -1.2 v i oh = -100
5 ics98ulpa877a advance information 1177c?05/23/07 notes: 1. unused inputs must be held high or low to prevent them from floating. 2. dc input signal voltage specifies the allowable dc execution of differential input. 3. differential inputs signal voltages specifies the differential voltage [vtr-vcp] required for switching, where vtr is the true input level and vcp is the complementary input level. 4. differential cross-point voltage is expected to track variations of v ddq and is the voltage at which the differential signal must be crossing. recommended operating condition ( see note1 ) commercial: ta = 0c - 70c; industrial: ta = -40c - +85c; supply voltage avddq, vddq = 1.8 v +/- 0.1v (unless otherwise stated) parameter symbol conditions min typ max units supply voltage v ddq , a vdd 1.7 1.8 1.9 v clk_int, clk_inc, fb_inc, fb_int 0.35 x v ddq v oe, os 0.35 x v ddq v clk_int, clk_inc, fb_inc, fb_int 0.65 x v ddq v oe, os 0.65 x v ddq v dc input signal voltage (note 2) v in -0.3 v ddq + 0.3 v dc - clk_int, clk_inc, fb_inc, fb_int 0.3 v ddq + 0.4 v ac - clk_int, clk_inc, fb_inc, fb_int 0.6 v ddq + 0.4 v output differential cross- voltage (note 4) v ox v ddq /2 - 0.10 v ddq /2 + 0.10 v input differential cross- voltage (note 4) v ix v ddq /2 - 0.15 v dd /2 v ddq 2 + 0.15 v high level output current i oh -9 ma low level output current i ol 9ma operating free-air temperature t a -40 85 c differential input signal voltage (note 3) v id low level input voltage v il high level input voltage v ih
6 ics98ulpa877a advance information 1177c?05/23/07 note: the pll must be able to handle spread spectrum induced skew. note: operating clock frequency indicates a range over which the pll must be able to lock, but in which it is not required to meet the other timing parameters. (used for low speed system debug.) note: application clock frequency indicates a range over which the pll must meet all timing parameters. note: stabilization time is the time required for the integrated pll circuit to obtain phase lock of its feedback signal to its reference signal, within the value specificied by the static phase offset ( t ? ), after power-up. during normal operation, the stabilization time is also the time required for the integrated pll circuit to obtain phase lock of its feedback signal to its reference signal when ck and ck# go to a logic low state, enter the power-down mode and later return to active operation. ck and ck# may be left floating after they have been driven low for one complete clock cycle. timing requirements commercial: ta = 0c - 70c; industrial: ta = -40c - +85c; supply voltage avddq, vddq = 1.8 v +/- 0.1v (unless otherwise stated) parameter symbol conditions min max units max clock frequency freq op 1.8v+ 0.1v @ 25c 95 410 mhz application frequency range freq app 1.8v+ 0.1v @ 25c 160 410 mhz input clock duty cycle d tin 40 60 % clk stabilization t stab 15 s
7 ics98ulpa877a advance information 1177c?05/23/07 notes: 1. switching characteristics guaranteed for application frequency range. 2. static phase offset shifted by design. switching characteristics 1 commercial: ta = 0c - 70c; industrial: ta = -40c - +85c; supply voltage avddq, vddq = 1.8 v +/- 0.1v (unless otherwise stated) parameter symbol condition (mhz) min typ max units output enable time t en oe to any output 4.73 8 ns output disable time t dis oe to any output 5.82 8 ns 160 to 270 -40 40 p s 271 to 410 -30 30 p s 160 to 270 -60 60 p s 271 to 410 -50 50 p s in p ut clock 1 2.5 4 v/ns output enable (oe), (os) 0.5 v/ns output clock slew rate slr1 ( o ) 1.5 2.5 3 v/ns t j it ( cc+ ) 040ps t j it ( cc- ) 0 -40 ps 160 to 270 -50 50 p s 271 to 410 -20 20 p s static phase offset t spo 2 271 to 410 -50 0 50 ps t jit (per) + t (?)dyn + t skew(o) (su) 80 ps t ( ? ) d y n + t skew ( o ) t ( h ) 60 ps 160 to 270 40 ps 271 to 410 30 p s ssc modulation fre q uenc y 30.00 33 khz ssc clock input frequency deviation 0.00 -0.50 % pll loop bandwidth (-3 db from unit y g ain) 2.0 mhz 160 to 410 period jitter t jit (per) input slew rate slr1(i) 160 to 410 cycle-to-cycle period jitter t (?)dyn half-period jitter t jit(hper) output to output skew t skew dynamic phase offset
8 ics98ulpa877a advance information 1177c?05/23/07 v dd gnd ics98ulpa877a v (clk) v (clk) v dd /2 v dd /2 ics98ulpa877a r=10 z=60 z=60 c = 10pf c = 10pf z=50 z=50 r=1m r=10 l = 2.97" l = 2.97" v tt v tt note: v tt =gnd c = 1pf r=1m c=1pf scope gnd z = 120 gnd yx, fb_outc yx, fb_outt t c(n) t c(n + 1) t jit(cc) =t c(n) +t c(n + 1) figure 1: ibis model output load figure 2: output load test circuit figure 3: cycle-to-cycle jitter parameter measurement information
9 ics98ulpa877a advance information 1177c?05/23/07 figure 4: static phase offset figure 5: output skew figure 6: period jitter clk_inc clk_int clk_inc clk_int t( ? )n t( ? )n+1 t( ? )= n=n 1 t( ? )n n yx# yx yx, fb_outc yx, fb_outt t skew yx, fb_outc yx, fb_outt yx, fb_outc yx, fb_outt t c(n) 1 fo t (jit_per) =t c(n) - 1 fo parameter measurement information
10 ics98ulpa877a advance information 1177c?05/23/07 figure 7: half-period jitter yx, fb_outc yx, fb_outt t jit(hper_n) 1 fo t jit(hper_n+1) t jit(hper) =t jit(hper_n) - 1 2xfo clock inputs and outputs 20% 80% t slr 20% 80% t slf v id v od figure 8: input and output slew rates parameter measurement information
11 ics98ulpa877a advance information 1177c?05/23/07 figure 9: dynamic phase offset figure 10: time delay between oe and clock output (y, y#) clk# clk fbin# fbin t( ? ) t( ? )dyn ssc off ssc on t( ? )dyn t( ? ) t( ? )dyn ssc off ssc on t( ? )dyn oe 50% v ddq t en 50% v ddq y. y# y# y oe 50% v ddq t dis 50% v ddq y# y
12 ics98ulpa877a advance information 1177c?05/23/07 v ddq gnd via card via card bead 0603 4.7uf 1206 0.1uf 0603 2200pf 0603 av dd agnd pll 1 figure 11. av dd filtering *place the 2200pf capacitors close to the pll. *use wide traces for pll analog power and gnd. connect pll and caps to agnd trace and connect trace to one gnd via (farthest from pll). *recommended bead: fair-rite p/n 2506036017y0 or equivalent (0.8 dc max., 600 at 100mhz).
13 ics98ulpa877a advance information 1177c?05/23/07 d e t e horiz vert total d h d1 e1 b c min/max min/max min/max 7.00 bsc 4.50 bsc 0.86/1.00 0.65 bsc 6 10 60 0.25/0.45 0.15/0.31 5.85 bsc 3.25 bsc 0.575 0.625 ** * source ref.: jedec publication 95, 10-0055 all dimensions in millimeters ref. dimensions ----- ball grid ----- max. note: ball g rid total indicates maximum ball count for packa g e. lesser quantity may be used. mo-205*, mo-225** seating plane 0.12 c c a b c d a1 d e top view t htyp dtyp 4321 numeric designations for horizontal grid bref cref typ -e- typ -e- d1 e1 alpha designations for vertical grid (letters i, o, q, and s not used) ordering information iCS98ULPA877AHLF-T example: designation for tape and reel packaging lead free, rohs compliant (optional) temperature grade blank = 0c to +70c (commercial) i = -40c to +85c (industrial) package type h = bga revision designator (will not correlate with datasheet revision) device type prefix ics = standard device ics xxxx y h z lf- t
14 ics98ulpa877a advance information 1177c?05/23/07 all dimensions in millimeters n symbol min. max. n d a 0.80 1.00 n e a1 0 0.05 d x e basic a3 d2 min. / max. b 0.18 0.30 e2 min. / max. e l min. / max. 10-0053 thermally enhanced, very thin, fine pitch quad flat / no lead plastic package 0.30 / 0.50 0.25 reference 0.50 basic 6.00 x 6.00 2.75 / 3.05 2.75 / 3.05 40 10 10 source reference: mlf2? s c 0.08 c seating plane a1 a3 a anvil singulation or sawn singulation n 1 2 index area e d top view l e2 e2/2 (n d -1)x e (ref.) n d &n e even (ref.) if n d &n e are even (typ.) e/2 1 2 b (n e -1)x e (ref.) thermal base n d &n e odd (ref.) e d2/2 d2 ordering information ics98ulpa877aklf-t example: designation for tape and reel packaging lead free, rohs compliant (optional) temperature grade blank = 0c to +70c (commercial) i = -40c to +85c (industrial) package type k = mlf revision designator (will not correlate with datasheet revision) device type prefix ics = standard device ics xxxx y k z lf- t

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